Design for Testability, Debug and Reliability

Next Generation Measures Using Formal Techniques de

,

Éditeur :

Springer


Paru le : 2021-04-19

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Description

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.
Pages
164 pages
Collection
n.c
Parution
2021-04-19
Marque
Springer
EAN papier
9783030692087
EAN PDF
9783030692094

Informations sur l'ebook
Nombre pages copiables
1
Nombre pages imprimables
16
Taille du fichier
4270 Ko
Prix
105,49 €
EAN EPUB
9783030692094

Informations sur l'ebook
Nombre pages copiables
1
Nombre pages imprimables
16
Taille du fichier
7598 Ko
Prix
105,49 €

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